Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction

High-Speed ADC with Error Correction

A digital error correction scheme is described for ADCs with multibit quantizers. It operates in the background and remains effective even for very low oversampling ratios.

Efficient Forward Error Correction for Reliable Transmission in Packet Networks

This paper proposes an approach that utilizes a new forward error correction mechanism for reconstructing lost or corrupted packets sent over a Network. Instead of retransmissions of lost or corrupted packets, the new approach depends on sending extra packets with each group of packets in order to reconstruct lost or corrupted packets. This approach is based on applying a high-performance irreg...

Efficient Forward Error Correction Decoder Design for High-Speed Optical Networking

Phase Frequency Detector Using Transmission Gates for High Speed Applications

In this paper a new phase-frequency detector is proposed using transmission gates which can detect phase difference less than 500ps. In other word, the proposed Phase-frequency Detector (PFD) can work in frequencies higher than 1.7 GHz, whereas a conventional PFD operates at frequencies less than 1.1 GHz. This new architecture is designed in TSMC 0.13um CMOS Technology. Also, the proposed PFD a...

Implementation of high-speed fixed-point dividers on FPGA

Study deals with implementations of fixed-point division modules based on different algorithms on basis of Xilinx FPGAs. We show that our implementation of the nonrestoring algorithm is significantly faster and smaller than the 32-bit IP Core “Pipelined Divider” from Xilinx. For example, the speed of the 32-bit designed module is almost 245 MHz vs. 193 MHz from Xilinx divider. Moreover, high-sp...